As an example of electrical/electronic devices, portable terminals refer to electronic devices that can be easily carried by making the size compact in order to perform functions such as game and mobile communication. Portable terminals can include, for example, mobile communication terminals, personal digital assistants (PDA) and portable multimedia players (PMP).
Among the portable terminals, the mobile communication terminal is essentially a device designed to enable a mobile user to telecommunicate with a receiver who is remotely located. Thanks to scientific development, however, the latest mobile communication terminals have functions, such as camera and multimedia data playback, in addition to the basic functions, such as voice communication, short message service and address book.
Portable terminals comprise a plurality of processors, including a main processor and at least one application processor, to perform multiple functions. The main processor controls the functions of the portable terminal and the operations of each application processor. The application processor performs predetermined additional functions (e.g. camera and multimedia data playback). In addition, portable terminals further comprise one or more memories to be connected to each processor.
The memories linked to the main processor include a NAND flash memory and a buffer memory. The NAND flash memory and buffer memory are integrated to one chip through the multi-chip package technology.
Below is a brief description with reference to FIG. 1 of connection structure and operation of processors in accordance with the prior art.
FIG. 1 is a diagram showing the connection structure between processors of the prior art. Although one application processor (a multimedia processor for processing multimedia data) is shown in FIG. 1, the number of application processors can vary as necessary.
Referring to FIG. 1, a portable terminal 100 of the prior art comprises a main processor 110, a memory chip 115, a multimedia platform 120, a sound output unit 125, an image sensor 130 and a display unit 135. The main processor 110, memory chip 115 and multimedia platform 120 can be realized in one chip, respectively.
The main processor 110 comprises a boot sequencer 140, a NAND interface 142, a cache memory 146, a processor core 148, an SD interface 150 (or a buffer interface) and a host interface 152.
To have the processor core 148 perform the booting, the boot sequencer 140 accesses a NAND flash memory 162 through the NAND interface 142 to read boot data and then delivers the read boot data to the processor core 148.
The processor core 148 performs a logic and/or operation pre-designated to function as the main processor 110. The process core 148 can comprise the cache memory 146 as a memory for performing the pre-designated logic or operation. Hereinafter, the processor core 148 included in the main processor 110 will be called the “main processor core.”
The NAND interface 142 interfaces with the NAND flash memory 162 included in the memory chip 115, and the SD interface 150 interfaces with a buffer memory 164 included in the memory chip 115. The host interface 152 interfaces with the multimedia platform 120.
The memory chip 115 comprises the NAND flash memory 162 and the buffer memory 164 in one chip through the multi-chip package technology.
The multimedia platform 120 comprises a multimedia processor 170 and a buffer memory 178 in one chip.
The multimedia processor 170 comprises a host interface 172 interfacing with the main processor 110, a processor core 174 performing a logic and/or operation pre-designated to function as the multimedia processor 170 and an SD interface 176 (or a buffer interface) interfacing with the buffer memory 178. Hereinafter, the processor core 174 included in the multimedia processor 170 will be called the “multimedia processor core.”
Coupled to the back of the multimedia platform 120 are the sound output unit 125, the image sensor 130 and the display unit 135.
The connection structure between processors shown in FIG. 1 is based on the related art and is familiar with anyone of ordinary skill in the art to which the invention pertains. Thus, further description will be omitted here.
Hereinafter, with reference to the connection structure of processors shown in FIG. 1, the booting sequence of the main processor 110 and the multimedia processor 120 will be briefly described.
The booting sequence of the main processor 110 is as follows:
Once the portable terminal 100 is powered on, the boot sequencer 140 accesses the NAND flash memory 162 in the memory chip 115 through the NAND interface 142.
The boot sequencer 140 reads boot data stored in an area of the NAND flash memory 162 and writes the boot data in the cache memory 146.
The boot sequencer 140 then delivers the boot data, stored in the cache memory 146, to the main processor core 148. Or, the processor core 148 can also read the boot data stored in the cache memory 146.
After booting through the use of the delivered boot data, the main processor core 148 reads the data for operating the portable terminal 100 that are stored in the NAND flash memory 162 through the NAND interface 142 and stores the data in the buffer memory 164 in the memory chip 115 accessed through the SD interface 150. The operating data stored in the NAND flash memory 162 is stored in the buffer memory 164 because the operating speed of the NAND flash memory 162 is slow.
Next, the booting sequence of the multimedia processor 170 is as follows:
The main processor core 148 reads the boot data stored in the NAND flash memory 162 in the memory chip 115 in order to have the multimedia processor core 174 perform the booting. If the main processor core 148 has already read the data and stored the data in the buffer memory 164, the data can be also read from the buffer memory 164.
The main processor core 148 delivers the read boot data to the multimedia processor core 174 through the host interface 152 and 172. The main processor core 148 can deliver the boot data, with a boot command, to the multimedia processor core 174.
After storing the received boot data in the buffer memory 178 through the SD interface 176, the multimedia processor core 174 performs the booting by use of the stored boot data.
As described above, to control the booting of the multimedia processor 170, the main processor 110 reads the needed data from the NAND flash memory 162 (or from the buffer memory 164) in the connected memory chip 115 and delivers the data to the multimedia processor core 174 through the host interface 152 and 172.
The above sequence is commonly applied to the multimedia data stored in the NAND flash memory 162 that needs to be delivered to the multimedia platform 120 for display through the display unit 135.
This, however, causes a drop in process efficiency of the main processor 110 while the main processor 110 is delivering the data to the multimedia platform 120. This can also cause a bottleneck problem while communicating the data between the host interfaces 152 and 172.
Moreover, including the three chips (i.e. main processor 110, memory chip 115 and multimedia platform 120), the portable terminal 100 has to be at least a certain size.
In other words, as the portable terminal 100 comprises more multimedia functions, more efficient integration is required.
As a result, the multi-chip package technology, in which the NAND flash memory 162 and the buffer memory 164 are combined in one chip, has been developed.
However, by preparing the multimedia platform 120 and the memory chip 115 separately, the there becomes less available space in a motherboard of the portable terminal 100, and as a result, it becomes difficult to include additional functions in a small size motherboard. This also inhibits the effort to make the portable terminal 100 smaller.